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Publications

Conference

VHDL

Pseudo Dual-Edge Flipflop: In special cases it might be useful to use both clock edges. Then a dual-edge flipflop is necessary. | Paper | LaTeX | VHDL |

Transfer-Gate: For the simulation of transfer-gates the signal has to be driven in both directions. To achieve this the driver must be set high-impedant, until the signals of the inputs are stable. Signal propagation over a chain of transfer-gate is a problem. One solution is waiting for several delta delays. | transfer-gate | testbench |

Studies

Student Research Project: (german) „FPGA-Implementierung der Quantisierung und Codierung des JPEG-Kompressionsalgorithmus| Studienarbeit | Verteidigung |

Diploma Thesis: (german) „Untersuchung und Entwicklung von Konzepten für eigensichere Sensorsysteme| Diplom | Verteidigung |

Dissertation: (german) „Softwaremethoden zur Senkung der Verlustenergie in Microcontrollersystemen| Dissertation | Verteidigung | publicated at: Fortschritt-Berichte VDI, Reihe 21: Elektrotechnik, 380, ISBN: 978-3-18-338021-3